Semiconductor device and method for manufacturing the same

ABSTRACT

The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent ApplicationNo. 2010-043192 filed on Feb. 26, 2010, the content of which is herebyincorporated by reference to this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a techniquefor manufacturing the same, and more particularly to a techniqueeffectively applied to a semiconductor device having an electrostaticcapacitor with a MIM (Metal Insulator Metal) structure in an integratedcircuit and to the manufacture of the same.

BACKGROUND OF THE INVENTION

In recent years, an electrostatic capacitor having a high capacitance,high accuracy and a low leakage current has been required in variousfilter circuits and analog-digital converter circuits incorporated inanalog-digital LSI (Large Scale Integrated circuit),transmitting/receiving circuits incorporated in RF (Radio Frequency)transmitting/receiving LSI, and others. Also, increase in theintegration of the electrostatic capacitor has also been required forreducing the cost of LSI.

As an electrostatic capacitor of this type, an electrostatic capacitorwith a so-called MIM structure in which a capacitance insulating film isdisposed between a pair of electrodes (a lower electrode and an upperelectrode) made of metal films formed on a semiconductor substrate isknown.

For example, IBM Journal Research and Development Vol. 47 No. 23 2/3Mar./May 2003, pp. 101 to 135 (Non-Patent Document 1) describes atechnique in which, after a metal film for a lower electrode, acapacitance insulating film and a metal film for an upper electrode aresequentially deposited on a semiconductor substrate, these films arepatterned by the dry etching using a photoresist film as a mask, therebyforming an electrostatic capacitor with a parallel-plate MIM structure.

Japanese Patent Application Laid-Open Publication No. 2008-210996(Patent Document 1) and Japanese Patent Application Laid-OpenPublication No. 2005-142435 (Patent Document 2) describe a manufacturingtechnique of an electrostatic capacitor in which an opening part isprovided in an interlayer insulating film on a lower electrode formed ona semiconductor substrate, and a capacitance insulating film and anupper electrode are formed in this opening part.

The method for manufacturing the electrostatic capacitor described inthe Patent Document 1 includes: a step of forming a first metal film(for example, an aluminum alloy film) on a first interlayer insulatingfilm of a semiconductor substrate; a step of forming a first upper-layerbarrier film (for example, a stacked film of a titanium film and atitanium nitride film) on the first metal film; a step of processing thefirst metal film and the stacked film of the first upper-layer barrierfilm, thereby forming first metal wiring and a lower electrode of theelectrostatic capacitor at the same time; a step of forming a secondinterlayer insulating film covering the first metal wiring and the lowerelectrode; a step of partially removing the second interlayer insulatingfilm, thereby exposing a part of an upper surface of the firstupper-layer barrier film constituting a part of the lower electrode; astep of forming a capacitance insulating film (for example, a siliconnitride film) of the electrostatic capacitor on the exposed firstbarrier film of the lower electrode; a step of forming a second metalfilm (for example, an aluminum alloy film) on the second interlayerinsulating film and the electrostatic capacitance insulating film; astep of forming a second upper-layer barrier film (for example, astacked film of a titanium film and a titanium nitride film) on thesecond metal film; and a step of processing the second metal film andthe stacked film of the second upper-layer barrier film, thereby formingsecond metal wiring and an upper electrode of the electrostaticcapacitor at the same time.

The method for manufacturing the electrostatic capacitor described inthe Patent Document 2 includes: a step of forming a first electrode (alower electrode) of the electrostatic capacitor made of a first-layermetal film (for example, a stacked film of a TiN film, an AlCu film anda TiN film) on a surface of an insulating film on a semiconductorsubstrate; a step of forming a first interlayer insulating film on thefirst electrode; a step of etching a part of the first interlayerinsulating film, thereby forming an opening part from which the surfaceof the first electrode is exposed; a step of depositing a dielectricfilm (for example, a silicon nitride film) and a second-layer metal film(for example, a stacked film of an AlCu film and a TiN film) on thefirst interlayer insulating film including the interior of the openingpart; and a step of polishing the second-layer metal film and thedielectric film by a chemical mechanical polishing (CMP) method, therebyforming a dielectric film and a second electrode (an upper electrode) ofthe electrostatic capacitor in the opening part.

Japanese Patent Application Laid-Open Publication No. 2007-201062(Patent Document 3) relates to a method for forming an electrostaticcapacitor with a MIS (Metal Insulator Silicide) structure and disclosesa method in which, after a lower electrode of the electrostaticcapacitor made of a metal silicide film (for example, Ni silicide) isformed on a semiconductor substrate, a capacitance insulating film madeof, for example, a nitride film and an upper electrode made of a metalfilm (for example, a Ni film) are formed in a recess part (a recess partwhose periphery is surrounded by an oxide film) on the lower electrode.

The above-described electrostatic capacitor is formed at the same timein the step of forming a gate electrode of an N-type MIS transistorhaving the stacked structure of the metal silicide film, the capacitanceinsulating film and the metal film. The capacitance insulating film andthe upper electrode of the electrostatic capacitor are formed bypolishing the capacitance insulating film and the metal film, which aredeposited on the oxide film including the interior of the recess part onthe lower electrode, by a CMP method, thereby causing the capacitanceinsulating film and the metal film to remain in the opening part.

SUMMARY OF THE INVENTION

FIG. 29 shows the technique disclosed in the Non-Patent Document 1described above, which corresponds to an electrostatic capacitorstructure (parallel-plate MIM capacitor) formed by sequentially stackinga capacitance insulating film and a metal film for an upper electrode ona lower electrode. The inventors of the present invention formed thedevice structure shown in FIG. 29 by applying the manufacturing methodshown in FIGS. 30A to 30D and then carried out the examination for thestructure.

First, as shown in FIG. 30A, an insulating film 51 such as a siliconoxide film is deposited on a semiconductor substrate 50, and then afirst metal film 52 a for the lower electrode, the capacitanceinsulating film 53 and a second metal film 54 a for the upper electrodeare sequentially deposited on the insulating film 51.

Next, as shown in FIG. 30B, the second metal film 54 a is patterned bythe dry etching using a photoresist film 100 as a mask, thereby formingan upper electrode 54. In this step, it is necessary to prevent thefirst metal film 52 a for the lower electrode from being etched in theetching for patterning the second metal film 54 a. Therefore, theprogress of the etching has to be stopped on the capacitance insulatingfilm 53. Herein, the reduction of the film thickness of the capacitanceinsulating film 53 is an effective method for forming a high-capacitancecapacitor, but the above-described dry etching becomes more difficult asthe capacitance insulating film 53 becomes thinner. This point is one ofthe problems included in the Non-Patent Document 1.

Next, as shown in FIG. 30C, the capacitance insulating film 53 and thefirst metal film 52 a are patterned by the dry etching using aphotoresist film 101 as a mask, thereby forming the lower electrode 52and first-layer wirings 56 and 57. Through the steps described above, anelectrostatic capacitor 55 made up of the lower electrode 52, thecapacitance insulating film 53 and the upper electrode 54 is completed.

Generally, the manufacturing cost of LSI can be reduced as the number ofwiring layers becomes smaller, and therefore, it is necessary to reducethe number of wiring layers as much as possible. Moreover, the increaseof the integration degree of each wiring is also effective for the costreduction of LSI. According to such points, it is desirable to form thelower electrode 52 at the same time as general wiring (first-layerwiring 56 and 57) such as power wiring and signal wiring. Moreover, thegeneral wiring is also required to have a high integration degree. Thereduction of the width and interval of the wirings, that is, theso-called microfabrication technique is required as a method forincreasing the integration of the wiring. In order to carry out themicrofabrication, the reduction of the thickness of a photoresist filmis required due to the physical restrictions of photolithographytechnique. Therefore, the photoresist film 101 for performing thepatterning of the first metal film 52 a has to completely cover theupper electrode 54 and surely has a sufficient film thickness inconsideration of the etching resistance capable of preventing the upperelectrode 54 from being exposed during the etching. In this respect,there is a problem that the establishment of a manufacturing method isdifficult.

Next, as shown in FIG. 30D, contact holes 60, 61 and 62 are formed in aninterlayer insulating film 58 covering the upper electrode 54, the lowerelectrode 52 and the first-layer wiring 57 so as to expose the surfacesof the upper electrode 54, the lower electrode 52 and the first-layerwiring 57, and then, metal plugs 63 are buried in the contact holes 60,61 and 62. Thereafter, second-layer wirings 64, 65 and 66 are formed onthe interlayer insulating film 58, thereby completing the structureshown in FIG. 29.

In the above-described parallel-plate electrostatic capacitor structure,since only the distance corresponding to the film thickness of thecapacitance insulating film 53 is ensured as the physical distancebetween the upper electrode 54 and the lower electrode 52, an electricfield is concentrated at an electrode end part, and the intensity of theelectric field is increased. However, the increase in the electric fieldintensity in an electrostatic capacitor causes the increase in a leakagecurrent and serves as a factor for the reduction of the breakdownvoltage characteristics. Therefore, it is difficult in this structure toachieve a highly stable high-capacitance electrostatic capacitorobtained by the reduction of the thickness of the capacitance insulatingfilm.

FIG. 31 shows the electrostatic capacitor structure (trench MIMcapacitor) of the Patent Document 1 in which an opening part is providedin an interlayer insulating film on a lower electrode, and a capacitanceinsulating film and an upper electrode are formed in the opening part.The inventors of the present invention formed the structure of FIG. 31by applying the manufacturing method shown in FIGS. 32A to 32D and FIGS.33A to 33C and then carried out the examination.

First, as shown in FIG. 32A, a first metal film 71 a for a lowerelectrode is deposited on a first interlayer insulating film 70deposited on a semiconductor substrate 50, and then, as shown in FIG.32B, the first metal film 71 a is patterned by the dry etching using aphotoresist film 103 as a mask, thereby forming the lower electrode 71and lower-layer wirings 72, 73 and 74.

Herein, the lower electrode 71 and the lower-layer wirings 72, 73 and 74are formed at the same time, but since it is unnecessary to change theprocesses from those of the case where only the lower-layer wirings 72,73 and 74 are formed, the processability of the lower electrode 71 isnot lowered unlike the case of forming the above-describedparallel-plate electrostatic capacitor.

Next, as shown in FIG. 32C, a second interlayer insulating film 75covering the lower electrode 71 and the lower-layer wirings 72, 73 and74 are deposited. Herein, the second interlayer insulating film 75 needsto be deposited so as to have the film thickness by which the lowerelectrode 71 and the lower-layer wirings 72, 73 and 74 can be completelycovered.

Next, as shown in FIG. 32D, the opening part 76 is formed in the secondinterlayer insulating film 75 by the dry etching using a photoresistfilm 104 as a mask, thereby exposing a part of the upper surface of thelower electrode 71.

Next, as shown in FIG. 33A, a capacitance insulating film 77 and asecond metal film 78 a for an upper electrode are sequentially stackedon the second interlayer insulating film 75 including the interior ofthe opening part 76. Then, as shown in FIG. 33B, the second metal film78 a and the capacitance insulating film 77 are patterned by the dryetching using a photoresist film 105 as a mask, thereby forming an upperelectrode 78 and a capacitance insulating film 77 covering the openingpart 76. Through the steps described above, the electrostatic capacitor79 made up of the lower electrode 71, the capacitance insulating film 77and the upper electrode 78 is completed.

Herein, since the second metal film 78 a and the capacitance insulatingfilm 77 are patterned by using photolithography technique, the diameterof the photoresist film 105 has to be larger than the diameter of theopening part 76 in consideration of misalignment of the photoresist film105 and the opening part 76. Therefore, the end parts of the capacitanceinsulating film 77 and the upper electrode 78 formed in the opening part76 are positioned outside the opening part 76 (on the second interlayerinsulating film 75).

Next, as shown in FIG. 33C, contact holes 80 and 81 are formed in thesecond interlayer insulating film 75 so as to expose the surfaces of thelower electrode 71 and the lower-layer wiring 74, and then, metal plugs82 are buried in the contact holes 80 and 81. Thereafter, second-layerwirings 83, 84 and 85 are formed on the interlayer insulating film 75,thereby completing the structure shown in FIG. 31.

In the above-described method for manufacturing the trench electrostaticcapacitor, the interlayer insulating film 75 below the upper electrode78 that is positioned outside the opening part 76 (on the secondinterlayer insulating film 75) functions as a capacitance insulatingfilm, and a parasitic capacitance is generated between the upperelectrode 78 on the second interlayer insulating film 75 and the lowerelectrode 71 below that. Since the parasitic capacitance can beconsidered as a capacitance parallelly connected to the electrostaticcapacitor 79, particularly in a fine electrostatic capacitor 79, thatis, the electrostatic capacitor 79 in which the area of the opening part76 is small, the electrostatic capacitance (capacitance density) perunit area appears to be large. Moreover, since the parasitic capacitancelike this is varied in accordance with manufacturing variations inphotolithography process, error accuracy cannot be estimated, and it isdifficult to form the fine electrostatic capacitor 79 at high accuracy.

The Patent Document 2 describes a technique in which, after theabove-described step shown in FIG. 33A, the second metal film 78 a andthe capacitance insulating film 77 on the second interlayer insulatingfilm 75 are polished and removed by using a chemical mechanicalpolishing method, thereby forming the capacitance insulating film 77 andthe upper electrode 78 in the opening part 76. However, in the case ofthis technique, if the flatness of the second interlayer insulating film75 is insufficient or if the opening parts 76 having different sizes arepresent in the second interlayer insulating film 75, there are problemsthat the second metal film 78 a remains on the second interlayerinsulating film 75 and that the upper electrode 78 (second metal film 78a) in the opening part 76 is polished more than necessary.

In the electrostatic capacitor with the MIS structure disclosed in thePatent Document 3, a metal silicide film is used as the material of alower electrode. However, since the metal silicide film is formed byreacting a polycrystalline silicon film with a metal film formedthereon, there is a problem that variations in the capacitance densityare increased due to, for example, irregularities on the surface of thepolycrystalline silicon film.

Japanese Patent Application Laid-Open Publication No. 2003-051501(Patent Document 4) discloses the formation of a MIM capacitor in amultilayer interconnection structure by using the dual damasceneprocess. However, since a metal film to be an upper electrode isdirectly electrically connected to upper-layer wiring in this structure,a parasitic capacitance is generated between the upper-layer wiring anda lower electrode (for example, FIG. 12 of Patent Document 4), and thereis a problem that the accuracy of the electrostatic capacitor is loweredas is described in relation to FIG. 31.

An object of the present invention is to provide a technique formanufacturing a high-capacitance and high-accuracy MIM electrostaticcapacitor by a small number of steps.

Another object of the present invention is to provide a technique forpromoting miniaturization of a high-capacitance and high-accuracy MIMelectrostatic capacitor.

The above and other objects and novel characteristics of the presentinvention will be apparent from the description of the presentspecification and the accompanying drawings.

The following is a brief description of an outline of the typicalinvention disclosed in the present application.

A method for manufacturing a semiconductor device which is one preferredaspect of the present invention is a method for manufacturing asemiconductor device having an electrostatic capacitor with a MIMstructure including a lower electrode, a capacitance insulating film andan upper electrode formed on a semiconductor substrate, and a step offorming the electrostatic capacitor includes: (a) a step of patterning afirst metal film formed on a first interlayer insulating film on thesemiconductor substrate, thereby forming the lower electrode; (b) a stepof forming a second interlayer insulating film on the first interlayerinsulating film and the lower electrode; (c) a step of forming anopening part in a part of the second interlayer insulating film, therebycausing a surface of the lower electrode to be exposed from a bottomsurface of the opening part; (d) a step of forming the capacitanceinsulating film so as to cover an upper part of the second interlayerinsulating film and a side wall and the bottom surface of the openingpart; (e) a step of sequentially forming a second metal film and aprotective metal film on the capacitance insulating film, therebyfilling the opening part with the protective metal film; (f) a step ofpolishing and removing the protective metal film, the second metal filmand the capacitance insulating film on the second interlayer insulatingfilm by a chemical mechanical polishing method, thereby causing thecapacitance insulating film, the upper electrode made of the secondmetal film and the protective metal film to remain in the opening part;and (g) a step of forming a third interlayer insulating film on thesecond interlayer insulating film.

The effects obtained by typical embodiments of the invention disclosedin the present application will be briefly described below.

According to the method for manufacturing the semiconductor device whichis a preferred aspect of the present invention, a high-capacitance andhigh-accuracy MIM electrostatic capacitor can be manufactured by a smallnumber of steps.

According to the method for manufacturing the semiconductor device whichis a preferred aspect of the present invention, miniaturization of thehigh-capacitance and high-accuracy MIM electrostatic capacitor can bepromoted.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a semiconductor device of afirst embodiment of the present invention;

FIG. 2 is a plan view showing a main part of the semiconductor device ofthe first embodiment of the present invention;

FIG. 3 is a perspective view showing a main part of the semiconductordevice of the first embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a main part of thesemiconductor device of the first embodiment of the present invention;

FIG. 5 is a cross-sectional view showing a method for manufacturing thesemiconductor device of the first embodiment of the present invention;

FIG. 6 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 5;

FIG. 7 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 6;

FIG. 8 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 7;

FIG. 9 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 8;

FIG. 10 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 9;

FIG. 11 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 10;

FIG. 12 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 11;

FIG. 13 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 12;

FIG. 14 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 13;

FIG. 15 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 14;

FIG. 16 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 15;

FIG. 17A is a graph showing the mismatch characteristics of thecapacitor of the comparative example 1;

FIG. 17B is a graph showing the mismatch characteristics of thecapacitor of the comparative example 2;

FIG. 17C is a graph showing the mismatch characteristics of the MIMcapacitor of the present invention;

FIG. 18 is a graph plotting the insulation breakdown resistance of aparallel-plate MIM capacitor and a trench MIM capacitor;

FIG. 19 is a cross-sectional view showing a main part of a semiconductordevice of a second embodiment of the present invention;

FIG. 20 is a cross-sectional view showing a method for manufacturing thesemiconductor device of the second embodiment of the present invention;

FIG. 21 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 20;

FIG. 22 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 21;

FIG. 23 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 22;

FIG. 24 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 23;

FIG. 25 is a cross-sectional view showing a method for manufacturing asemiconductor device of a third embodiment of the present invention;

FIG. 26 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 25;

FIG. 27 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 26;

FIG. 28 is a cross-sectional view showing the method for manufacturingthe semiconductor device continued from FIG. 27;

FIG. 29 is a cross-sectional view showing a conventional parallel-plateMIM capacitor studied by the inventors of the present invention;

FIG. 30A is a cross-sectional view showing a method for manufacturingthe conventional parallel-pate MIM capacitor studied by the inventors ofthe present invention;

FIG. 30B is a cross-sectional view showing a method for manufacturingthe conventional parallel-pate MIM capacitor studied by the inventors ofthe present invention;

FIG. 30C is a cross-sectional view showing a method for manufacturingthe conventional parallel-pate MIM capacitor studied by the inventors ofthe present invention;

FIG. 30D is a cross-sectional view showing a method for manufacturingthe conventional parallel-pate MIM capacitor studied by the inventors ofthe present invention;

FIG. 31 is a cross-sectional view showing a conventional trench MIMcapacitor studied by the inventors of the present invention;

FIG. 32A is a cross-sectional view showing a method for manufacturingthe conventional trench MIM capacitor studied by the inventors of thepresent invention;

FIG. 32B is a cross-sectional view showing a method for manufacturingthe conventional trench MIM capacitor studied by the inventors of thepresent invention;

FIG. 32C is a cross-sectional view showing a method for manufacturingthe conventional trench MIM capacitor studied by the inventors of thepresent invention;

FIG. 32D is a cross-sectional view showing a method for manufacturingthe conventional trench MIM capacitor studied by the inventors of thepresent invention;

FIG. 33A is a cross-sectional view showing the method for manufacturingthe trench MIM capacitor continued from FIG. 32D;

FIG. 33B is a cross-sectional view showing the method for manufacturingthe trench MIM capacitor continued from FIG. 33A; and

FIG. 33C is a cross-sectional view showing the method for manufacturingthe trench MIM capacitor continued from FIG. 33B.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that componentshaving the same function are denoted by the same reference symbolsthroughout the drawings for describing the embodiments, and therepetitive description thereof will be omitted. In addition, thedescription of the same or similar portions is not repeated in principleunless particularly required in the following embodiments. Also, in thedrawings for describing the embodiments, hatching is used even in a planview so as to make the structure easily understood.

First Embodiment

FIG. 1 is a cross-sectional view showing a main part of a semiconductordevice of the present embodiment. As shown in FIG. 1, n channel MISFETs(Metal Insulator Semiconductor Field Effective Transistors) Qn and pchannel MISFETs Qp are formed on a semiconductor substrate 10 made ofsingle crystal silicon, and first-layer wirings 12, 13, 14, 15 and 16are formed above the n channel MISFETs Qn and the p channel MISFETs Qpvia an insulating film 11. Moreover, second-layer wirings 20, 22 and 23and a lower electrode 21 are formed above the first-layer wirings 12 to16 via a first interlayer insulating film 17.

A second interlayer insulating film 24 is formed on the second-layerwirings 20, 22 and 23 and the lower electrode 21, and an opening part 34on a bottom surface of which the lower electrode 21 is exposed is formedin the second interlayer insulating film 24 on the lower electrode 21.Moreover, in the opening part 34, a capacitance insulating film 27, anupper electrode 28 and a protective metal film 29 are buried in thisorder from the lower layer thereof.

The lower electrode 21 formed in the layer below the opening part 34,the capacitance insulating film 27, the upper electrode 28 and theprotective metal film 29 formed in the opening part 34 constitute anelectrostatic capacitor 25 with a MIM structure.

A third interlayer insulating film 30 is formed on the second interlayerinsulating film 24 and the opening part 34, and a contact hole 35 isformed in the third interlayer insulating film 30 on the protectivemetal film 29 buried in the opening part 34. The protective metal film29 is connected to third-layer wiring 31 on the third interlayerinsulating film 30 via a metal plug 38 formed in the contact hole 35.

Moreover, third-layer wirings 32 and 33 are formed together with thethird-layer wiring 31 on the third interlayer insulating film 30. Sincethe upper electrode 28 and the protective metal film of theelectrostatic capacitor 25 are separated from the third-layer wiring 31by the second interlayer insulating film 24, no problem is caused evenwhen the wiring (third-layer wirings 32 and 33) other than thethird-layer wiring 31 is disposed above the electrostatic capacitor 25.

Two contact holes 36 and 37 are formed in the third interlayerinsulating film 30 and the second interlayer insulating film 24 whichare the layers below the third-layer wiring 32. The third-layer wiring32 is connected to the lower electrode 21 of the electrostatic capacitor25 via the metal plug 38 in the contact hole 36, and is connected to thesecond-layer wiring via the metal plug 38 in the contact hole 37.

In the following drawings, the illustration of the region below thefirst interlayer insulating film 17 is omitted, and only the firstinterlayer insulating film 17 and the region above the first interlayerinsulating film 17 are shown.

FIG. 2 is a plan view showing the second-layer wiring 21, theelectrostatic capacitor 25 and the third-layer wirings 31 and 32 viewedfrom above. FIG. 2 shows three electrostatic capacitors 25 each havingthe same structure as the above-described electrostatic capacitor 25,and FIG. 1 shows the region in which one of these is formed. The planarshape of the opening part 34 in which the electrostatic capacitor 25 isformed can be arbitrarily changed to a square, a rectangle or the likein accordance with the layout of the second-layer wirings 20 to 23. FIG.3 is a perspective view showing the second-layer wiring 21, theelectrostatic capacitor 25, the contact hole 35 and the third-layerwiring 31 viewed from above, and FIG. 4 is a cross-sectional viewshowing a part of FIG. 1 in an enlarged manner.

Next, a method for manufacturing the semiconductor device having theelectrostatic capacitor 25 will be described in the order of steps withreference to FIG. 5 to FIG. 16. Note that, since the process from thestep of forming the n channel MISFETs Qn and the p channel MISFETs Qpshown in FIG. 1 to the step of forming the first-layer wirings 12 to 16can be carried out in accordance with an ordinary method, thedescriptions thereof are omitted.

FIG. 5 shows the state in which the first interlayer insulating film 17is deposited on the first-layer wirings 12 to 16 shown in FIG. 1. Thefirst interlayer insulating film 17 is made of, for example, a siliconoxide film deposited by a CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 6, after a first metal film 40 is deposited onthe first interlayer insulating film 17, a BARL (Bottom Anti ReflectionLayer) film 41 is deposited on the first metal film 40. The first metalfilm 40 is made of, for example, a titanium nitride film, an aluminumalloy film and a titanium nitride film deposited by a sputtering method.The BARL film 41 is an anti-reflection film for preventing abnormalexposure of a photoresist film caused by the exposure light transmittedthrough the photoresist film and reflected by the surface of the firstmetal film 40 in the exposure of the photoresist film formed on thefirst metal film 40 in the next step. The BARL film 41 is made of, forexample, a silicon oxynitride film deposited by a CVD method. Similareffects can be obtained also when a BARC (Bottom Anti Reflection Coat)film, a TARC (Top Anti Reflection Coat) film or the like is used insteadof the BARL film 41 or together with the EARL film 41. If theabove-described abnormal exposure of the photoresist film is negligible,there is no need to use these anti-reflection films.

Next, as shown in FIG. 7, a photoresist film 106 applied on the EARLfilm 41 is subjected to exposure and development, thereby causing thephotoresist film 106 to remain in a first-layer wiring forming regionand a lower electrode forming region. Subsequently, as shown in FIG. 8,the EARL film 41 and the first metal film 40 are patterned by the dryetching using the photoresist film 106 as a mask, thereby forming thelower electrode 21 and the second-layer wiring 22.

Next, after the photoresist film 106 is removed, as shown in FIG. 9, thesecond interlayer insulating film 24 is deposited on the lower electrode21 and the second-layer wiring 22, and subsequently, the surface of thesecond interlayer insulating film 24 is planarized by using a CMPmethod. The second interlayer insulating film 24 is made of, forexample, a silicon oxide film deposited by a CVD method.

Next, as shown in FIG. 10, the second interlayer insulating film 24 andthe EARL film 41 on the lower electrode 21 are subjected to dry etchingwith using a photoresist film 107, which is formed on the secondinterlayer insulating film 24, as a mask, thereby forming the openingpart 34 from which the surface of the lower electrode 21 is exposed. Theopening part 34 is an open-topped recess with an approximately U-shapedcross section, and the depth thereof is equal to the height from thesurface of the lower electrode 21 to the flat surface of the secondinterlayer insulating film 24. Through the steps described above, thesurface of the semiconductor substrate 10 has a flat structure having arecess only in the region in which the opening part 34 is formed.

Next, after the photoresist film 107 is removed, as shown in FIG. 11,the capacitance insulating film 27 is deposited so as to cover the upperpart of the second interlayer insulating film 24 and the bottom surfaceand the side surface of the opening part 34. The capacitance insulatingfilm 27 is made of, for example, a silicon nitride film deposited by aCVD method. Alternatively, the capacitance insulating film 27 may bemade of an insulating film having a dielectric constant higher than thatof a silicon nitride film such as a tantalum oxide film or a hafniumoxide film.

Next, as shown in FIG. 12, a second metal film 42 for the upperelectrode is deposited on the capacitance insulating film 27, andsubsequently, the protective metal film 29 is deposited on the secondmetal film 42. The second metal film 42 is made of, for example, atitanium nitride film deposited by a sputtering method, and theprotective metal film 29 is made of, for example, a tungsten filmdeposited by a CVD method. Also, the protective metal film 29 isdeposited so as to have a large film thickness by which the interior ofthe opening part 34 is completely filled.

A metal compound film made of tantalum nitride or a metal film made ofcopper, aluminum or tungsten may be used as the second metal film 42 forthe upper electrode instead of the titanium nitride film, but in orderto form a high-accuracy MIM capacitor, it is desirable to use a materialhaving a resistivity equivalent to that of the lower electrode 21. Also,a metal film made of aluminum or copper or a metal compound film made oftitanium nitride may be used as the protective metal film 29 instead ofthe tungsten film, but the material having the property that it can bepolished and removed together with the second metal film 42 in the nextCMP processing step is used.

Next, as shown in FIG. 13, the protective metal film 29, the secondmetal film 42 and the capacitance insulating film 27 on the secondinterlayer insulating film 24 are polished and removed by using a CMPmethod, thereby causing these films to remain only in the opening part34. At this point, the upper surfaces of the protective metal film 29,the second metal film 42 and the capacitance insulating film 27remaining in the opening part 34 have the same height as the surface ofthe second interlayer insulating film 24. Through the steps describedabove, the electrostatic capacitor 25 with the MIM structure made up ofthe lower electrode 21 formed in the layer below the opening part 34 andthe capacitance insulating film 27, the upper electrode 28 (second metalfilm 42) and the protective metal film 29 formed in the opening part 34is completed.

Next, as shown in FIG. 14, the third interlayer insulating film 30 isdeposited on the second interlayer insulating film 24 and theelectrostatic capacitor 25. The third interlayer insulating film 30 ismade of, for example, a silicon oxide film deposited by a CVD method.Since the third interlayer insulating film 30 is deposited on the flatsecond interlayer insulating film 24, the surface thereof becomes flateven when the surface is not subjected to CMP.

Next, as shown in FIG. 15, the third interlayer insulating film 30 onthe protective metal film 29 is subjected to dry etching with using aphotoresist film 108, which is formed on the third interlayer insulatingfilm 30, as a mask, thereby forming the contact hole 35. Also, at thistime, the third interlayer insulating film 30, the second interlayerinsulating film and the EARL film 41 on the lower electrode 21 aresubjected to dry etching, thereby forming the contact hole 36, and thethird interlayer insulating film 30, the second interlayer insulatingfilm and the BARL film 41 on the second-layer wiring 22 are subjected todry etching, thereby forming the contact hole 37. Then, the metal plugs38 are formed in the contact holes 35, 36 and 37. In order to form themetal plugs 38, for example, a metal film made of a tungsten film or atitanium nitride film is deposited on the third interlayer insulatingfilm 30 and in the contact holes 35, 36 and 37 by a sputtering method ora CVD method, and subsequently, the metal film on the third interlayerinsulating film 30 is polished and removed by a CMP method.

Next, as shown in FIG. 16, the third-layer wirings 31 and 32 are formedon the third interlayer insulating film 30. The material and the formingmethod of the third-layer wirings 31 and 32 may be the same as those ofthe lower electrode 21 and the second-layer wiring 22. Since the surfaceof the third interlayer insulating film 30 is sufficiently flat, it isfree from irregularities, which cause problems when fine etching iscarried out. Therefore, the wiring density of the third-layer wirings 31and 32 can be increased. Through the steps described above, thesemiconductor device shown in FIG. 1 is completed.

Next, effects of the present invention will be described. FIGS. 17A to17C are graphs showing the mismatch characteristics of the MIM capacitorof the present invention manufactured by the above-described method, thecomparative example 1 (the parallel-plate MIM capacitor described withreference to FIG. 29 and FIGS. 30A to 30D) and the comparative example 2(the trench MIM capacitor described with reference to FIG. 31 to FIG.33C). The graph of FIG. 17A shows the mismatch coefficients of thecomparative example 1, the graph of FIG. 17B shows the mismatchcoefficients of the comparative example 2, and the graph of FIG. 17Cshows the mismatch coefficients of the MIM capacitor of the presentinvention.

In each of the graphs of FIGS. 17A, 17B and 17C, the horizontal axisrepresents the reciprocal of the square root of the designed area of theMIM capacitor, and the vertical axis plots the value (capacitancemismatch) obtained by dividing the difference in the electrostaticcapacitances of adjacent MIM capacitors by the average value thereof.Specifically, the capacitance mismatch becomes smaller as the variationsof the adjacent MIM capacitors are reduced. The points in each of thegraphs represent the plotted values obtained by measuring thecapacitance mismatch in the MIM capacitors having various areas. In eachof the graphs, the slope of the vertical axis (capacitance mismatch)with respect to the horizontal axis (the reciprocal of the square rootof the area) is referred to as a capacitance mismatch coefficient. Thecapacitance mismatch coefficient is generally used as an evaluationindex of the variation accuracy of capacitors, and the capacitor withthe smaller capacitance mismatch coefficient means thehigher-performance capacitor with smaller variations.

As shown in the graphs of FIGS. 17A, 17B and 17C, the mismatchcoefficient of the comparative example 1 (the parallel-plate MIMcapacitor) is 0.48, the mismatch coefficient of the comparative example2 (the trench MIM capacitor) is 0.74, and the mismatch coefficient ofthe MIM capacitor according to the present invention is 0.41. The reasonwhy the mismatch coefficient of the comparative example 2 issignificantly large is that, as described above, the end part of theupper electrode is positioned on the interlayer insulating film outsidethe opening part due to the variations in the mask position accuracycaused by the formation using photolithography technique and dry etchingtechnique, and the parasitic capacitance is generated between that andthe wiring in the lower layer via the interlayer insulating film (seeFIGS. 33A to 33C). Then, since the capacitance value of the MIMcapacitor is reduced as the diameter of the trench (opening part)becomes smaller and the influence of the parasitic capacitance withrespect to the capacitance value of the MIM capacitor is relativelyincreased, the variations in the parasitic capacitance becomenonnegligible large values.

The parasitic capacitance value of the conventional trench MIM capacitordepends on the area of the manufactured MIM capacitor, in other words,the bottom area of the trench (opening part) and the processing accuracyof the upper electrode, and in the structure studied by the inventors ofthe present invention, it has the influence of up to about 3 to 4%.

On the other hand, in the parallel-plate MIM capacitor and the structureof the present invention in which the upper electrode and the lowerelectrode are not opposed to each other in the region other than theregion in which the MIM capacitor is formed, the parasitic capacitancedescribed above is not generated, and therefore, a high-accuracy MIMcapacitor with small variations can be formed.

FIG. 18 is a graph plotting the insulation breakdown resistance of theparallel-plate MIM capacitor and the trench MIM capacitor. Thehorizontal axis represents the electric field intensity applied to theMIM capacitor per 1 cm of the thickness of the capacitance insulatingfilm. The vertical axis represents the cumulative value of the MIMcapacitor area in which the capacitance insulating film reaches itsinsulation breakdown when a DC voltage is applied to the MIM capacitor.The horizontal axis is referred to as “breakdown voltage”, and thevertical axis is referred to as “cumulative defect density”. In otherwords, FIG. 18 is a drawing plotting the area of the MIM capacitor whichreaches its breakdown when a voltage is applied, and the drawing showsthat the element having the smaller cumulative defect density at thesame breakdown voltage is the MIM capacitor having higher stability.

As shown in FIG. 18, when the breakdown voltage is 5.5 MV/cm or lower,there is a large difference in the cumulative defect density between theparallel-plate MIM capacitor and the trench MIM capacitor of the presentinvention. For example, when compared at a breakdown voltage of 5.0 V,the cumulative defect density of the parallel-plate MIM capacitor is1.74/cm², while that of the trench MIM capacitor of the presentinvention is 0.42/cm².

As shown in FIG. 29, in the parallel-plate MIM capacitor, only thedistance corresponding to the film thickness of the capacitanceinsulating film 53 is ensured as the physical distance between the endpart of the upper electrode 54 and the surface of the lower electrodelayer 52 where electric field concentration may occur. Also, when theelectrostatic capacitor 55 is covered with the interlayer insulatingfilm 58, the end part of the upper electrode 54 and the surface of thelower electrode 52 are in contact with the same insulating filminterface which is inferior in insulation properties, and this serves asa factor for the increase of the leakage current.

On the other hand, in the structure of the present invention, as shownin FIG. 4, the end part of the upper electrode 28 is not in contact withthe lower electrode 21, and the distance corresponding to the leveldifference of the opening part 34, in other words, the height of thesurface of the upper electrode 28 and the upper surface of theinterlayer insulating film 24 is ensured as the physical distancetherebetween. Since the distance from the electrode end part at whichthe insulation breakdown readily occurs is physically sufficient in thisstructure, it can be said that the insulation breakdown resistance isgood.

The above-described two points are the effects of the capacitorstructure of the present invention. Furthermore, there are the followingtwo points as additional effects.

The capacitance insulating film of the trench MIM capacitor has smallrestrictions with respect to the film thickness and the film qualitythereof as is clear from the manufacturing method thereof. On the otherhand, the parallel-plate MIM capacitor studied by the inventors of thepresent invention has restrictions in the film thickness of thecapacitance insulating film because of the electric field concentrationat the end part of the upper electrode and the above-describedrestrictions in the processing of the upper electrode. Regarding thispoint, a capacitor having a higher electrostatic capacitance can beformed by the trench MIM capacitor.

Moreover, since the lower electrode can be formed in the step ofprocessing the wiring of the same layer as described above, there is noneed to form a particular wiring layer or the like. Therefore, theincrease in the integration of LSI and the reduction in the number ofwiring layers can be expected, and the manufacturing cost of LSI can bereduced.

In a semiconductor device in which an analog-digital circuit is mounted,a generally-well-known pipeline-type analog-digital converter circuit orsuccessive-approximation type analog-digital converter circuit ismounted, and a high-capacitance and high-accuracy electrostaticcapacitor is indispensable for improving the performance of such ananalog-digital converter circuit. Therefore, it can be said that thecapacitor structure of the present invention can be effectively appliedto a capacitor mounted in such a circuit.

Second Embodiment

In the above-described first embodiment, the first metal film (forexample, a stacked film of a titanium nitride film, an aluminum alloyfilm and a titanium nitride film) is processed at the same time to formthe lower electrode 21 of the electrostatic capacitor 25 and thesecond-layer wiring 22. However, one of the characteristics of thepresent invention lies in that the formation of the electrostaticcapacitor 25 does not affect the formation processes of the wiring(second-layer wiring 22) in the same layer as the lower electrode 21 andthe wiring (third-layer wirings 31 and 32) in the upper layer of thelower electrode 21. Therefore, the lower electrode 21, the second-layerwiring 22 and the third-layer wirings 31 and 32 may be formed of a metalmaterial that is different from the first metal film 40.

FIG. 19 is a cross-sectional view in which the lower electrode 21, thesecond-layer wiring 22 and the third-layer wirings 31 and 32 are formedby the so-called damascene process utilizing a CMP method. Hereinafter,a method of forming the wiring by the damascene process will bedescribed with reference to FIG. 20 to FIG. 24. Like the above-describedfirst embodiment, in the following drawings, the illustration of theregion below the first interlayer insulating film 17 is omitted, andonly the first interlayer insulating film 17 and the region above thefirst interlayer insulating film 17 are shown.

First, as shown in FIG. 20, after wiring trenches 43 and 44 are formedin the first interlayer insulating film 17, a barrier metal film 45 isdeposited on the first interlayer insulating film 17 and in the wiringtrenches 43 and 44, and subsequently, a copper film 46 is formed on thebarrier metal film 45 by using a plating method. The wiring trenches 43and 44 are formed by performing the dry etching of the first interlayerinsulating film 17 with using a photoresist film (not shown) as a mask.The barrier metal film 45 is made of, for example, a tantalum nitridefilm deposited by a sputtering method. The copper film 46 is formed soas to have a large film thickness by which the interiors of the wiringtrenches 43 and 44 are completely filled.

Next, as shown in FIG. 21, the copper film 46 and the barrier metal film45 on the first interlayer insulating film 17 are polished and removedby using a CMP method, thereby causing these films to remain only in thewiring trenches 43 and 44. At this point, the upper surfaces of thecopper film 46 and the barrier metal film 45 remaining in the wiringtrenches 43 and 44 have the same height as the surface of the firstinterlayer insulating film 17. In this manner, the lower electrode 21made of the stacked film of the barrier metal film 45 and the copperfilm 46 is formed in the wiring trench 43, and the second-layer wiring22 made of the stacked film of the barrier metal film 45 and the copperfilm 46 is formed in the wiring trench 44.

Next, as shown in FIG. 22, after a diffusion preventing film 47 isdeposited on the first interlayer insulating film 17, the lowerelectrode 21 and the second-layer wiring 22, the second interlayerinsulating film 24 is deposited on the diffusion preventing film 47. Thediffusion preventing film 47 is an insulating film which prevents thecopper components constituting each part of the lower electrode 21 andthe second-layer wiring 22 from being diffused into the secondinterlayer insulating film 24 and is made of, for example, a siliconnitride film or an oxygen-added silicon carbide film deposited by a CVDmethod. The second interlayer insulating film 24 is made of, forexample, a silicon oxide film or a carbon-added silicon oxide filmdeposited by a CVD method. Since the second interlayer insulating film24 is deposited on the flat first interlayer insulating film 17, thesurface thereof becomes flat even when the surface is not subjected toCMP.

Next, as shown in FIG. 23, after the opening part 34 is formed in thesecond interlayer insulating film 24 and the diffusion preventing film47 on the lower electrode 21, the electrostatic capacitor 25 with theMIM structure made up of the capacitance insulating film 27, the upperelectrode 28 and the protective metal film 29 is formed in the openingpart 34. The method for forming the opening part 34 and the method forforming the electrostatic capacitor 25 may be the same as thosedescribed in the first embodiment (see FIG. 10 to FIG. 13). As thecapacitance insulating film 27 of the electrostatic capacitor 25, thematerial shown as an example in the above-described first embodiment isused, but the material capable of preventing diffusion of the coppercomponent in the lower electrode 21 is desirable. As the upper electrode28 and the protective metal 29, the materials shown as examples in theabove-described first embodiment are used.

Next, as shown in FIG. 24, after the third interlayer insulating film 30is deposited on the second interlayer insulating film 24 and theelectrostatic capacitor 25, wiring trenches 48 and 49 are formed in thethird interlayer insulating film 30. Moreover, the contact hole 35 isformed in the third interlayer insulating film 30 below the wiringtrench 48, and the contact holes 36 and 37 are formed in the thirdinterlayer insulating film 30, the second interlayer insulating film 24and the diffusion preventing film 47 below the wiring trench 49. Thewiring trenches 48 and 49 and the contact holes 35, 36 and 37 are formedby the dry etching using photoresist films (not shown) as masks. Eitherthe wiring trenches 48 and 49 or the contact holes 35, 36 and 37 may beformed first. When the protective metal film 29 of the electrostaticcapacitor 25 is made of copper, a diffusion preventing film having thesame composition as the diffusion preventing film 47 is deposited in thelayer below the third interlayer insulating film 30 in order to preventcopper components from being diffused into the third interlayerinsulating film 30.

Then, the third-layer wirings 31 and 32 are buried in the wiringtrenches 48 and 49 and the contact holes 35, 36 and 37 by the damasceneprocess, thereby completing the wiring structure shown in FIG. 19. Thematerial and the forming method of the third-layer wirings 31 and 32 maybe the same as those of the above-described lower electrode 21 and thesecond-layer wiring 22.

Third Embodiment

In the above-described first and second embodiments, the capacitanceinsulating film 27, the upper electrode 28 and the protective metal film29 of the electrostatic capacitor 25 are buried in the opening part 34.However, in the present embodiment, a process for causing a part of thecapacitance insulating film 27 to remain outside the opening part 34 (onthe surface of the second interlayer insulating film 24) will bedescribed.

First, as shown in FIG. 25, the opening part 34 is formed in the secondinterlayer insulating film 24 on the lower electrode 21, and then, thecapacitance insulating film 27 is deposited so as to cover the upperpart of the second interlayer insulating film 24 and the bottom surfaceand the side surface of the opening part 34. Subsequently, after thesecond metal film 42 for the upper electrode is deposited on thecapacitance insulating film 27, the protective metal film 29 isdeposited on the second metal film 42. The steps above are the same asthose shown in FIG. 5 to FIG. 12 of the above-described firstembodiment.

Next, as shown in FIG. 26, the protective metal film 29 and the secondmetal film 42 on the second interlayer insulating film 24 are polishedand removed by using a CMP method. In this CMP, polishing is stopped atthe point when the second metal film 42 on the second interlayerinsulating film 24 is polished and removed to cause the capacitanceinsulating film 27 to remain on the second interlayer insulating film24. Through the steps described above, the capacitance insulating film27, the upper electrode 28 (second metal film 42) and the protectivemetal film 29 are buried in the opening part 34, and the electrostaticcapacitor 25 with the MIM structure is completed.

In the above-described method for forming the capacitor 25, thecapacitance insulating film 27 remains on the surface of the secondinterlayer insulating film 24. However, since the protective metal film29 and the second metal film 42 on the surface of the second interlayerinsulating film 24 are removed, the problem of the parasitic capacitancecaused in the above-described trench MIM capacitor structure of thePatent Document 1 does not occur. Therefore, the subsequent steps (thesteps after FIG. 14 of the above-described first embodiment) may becarried out in the state in which the capacitance insulating film 27remains on the surface of the second interlayer insulating film 24.

However, when the capacitance insulating film 27 remains on the surfaceof the second interlayer insulating film 24, the subsequent etching ofthe second interlayer insulating film 24 in the step of forming thecontact holes 36 and 37 (see FIG. 15) becomes cumbersome. Moreover, whenthe capacitance insulating film 27 having a high dielectric constantremains on the surface of the second interlayer insulating film 24, theparasitic capacitance between the second-layer wiring 22 and thethird-layer wiring 32 is increased.

Therefore, when such a problem is conceivable, it is preferable to carryout the subsequent steps after removing the capacitance insulating film27 on the second interlayer insulating film 24 by the dry etching usingthe photoresist film 108 as a mask as shown in FIG. 27. In this case,however, since the capacitance insulating film 27 on the secondinterlayer insulating film 24 is removed by using photolithographytechnique, the diameter of the photoresist film 108 has to be largerthan the diameter of the opening part 34 in consideration of themisalignment between the photoresist film 108 and the opening part 34.Therefore, although the capacitance insulating film 27 slightly remainson the second interlayer insulating film 24 around the opening part 34,the formation of the contact holes 36 and 37 does not become cumbersome.Also, the increase in the parasitic capacitance between the second-layerwiring 22 and the third-layer wiring 32 is extremely small.

Thereafter, as shown in FIG. 28, the third interlayer insulating film30, the contact holes 35, 36 and 37 and the metal plugs 38 are formed bythe same method as the above-described first embodiment, and then, thethird-layer wirings 31 and 32 are formed on the third interlayerinsulating film 30.

In the above-described capacitor structure, the capacitance insulatingfilm 27 remaining on the surface of the second interlayer insulatingfilm 24 is present only in the vicinity of the opening part 34, andtherefore, a large parasitic capacitance is not generated and thecharacteristic of the present invention that the parasitic capacitancecan be reduced is maintained.

In recent years, development of a MIM capacitor having a highercapacitance has been desired. When a material having a high dielectricconstant such as a hafnium oxide or a tantalum oxide is used as acapacitance insulating film material, it is difficult to polish andremove the capacitance insulating film together with the upper electrodematerial (second metal film 42) and the protective metal film 29, andtherefore, the capacitance insulating film remains on the interlayerinsulating film 24 in some cases.

In this case, when the contact holes 35 to 37 are formed in the layer onthe capacitor 25, the stacked film made up of the third interlayerinsulating film 30, the capacitance insulating film 27 and the secondinterlayer insulating film 24 has to be processed in order to expose thesecond-layer wiring 22 and the lower electrode 21. Also, as theinterlayer insulating film formed between the upper and lower wiringlayers, a material having a low dielectric constant is selected ingeneral in order to reduce the parasitic capacitance between the wiringlayers. On the other hand, in order to achieve the capacitance increaseof the MIM capacitor, it is desirable to select an interlayer insulatingfilm having a high dielectric constant. Therefore, in many cases,different insulating materials are stacked in the stacked film made upof the upper interlayer insulating film, the capacitance insulating filmand the lower interlayer insulating film. Accordingly, in the step offorming the contact holes 35 to 37 by using dry etching technique, amethod for changing the gas or the like used in dry etching during theprocess and a method capable of dry-etching different films at the sametime have to be used, and processing becomes extremely cumbersome.

The above-described capacitor structure of the present embodiment hasthe effect of solving such problems. Also, in order to reduce theparasitic capacitance between the upper and lower wiring layers, thereduction of the dielectric constant of the interlayer insulating filmprovided between the wiring layers is effective. In the above-describedcapacitor structure, since the capacitance insulating film 27 on thesurface of the second interlayer insulating film 24 remains only in thevicinity of the opening part 34, the effect of reducing the parasiticcapacitance between the wiring layers can also be obtained. In the caseof the above-described first embodiment, in order to obtain the effect,when the protective metal film 29, the second metal film 42 for theupper electrode and the capacitance insulating film 27 are to bepolished by using a CMP method, the capacitance insulating film 27 whichcan be polished at the same time as the protective metal film 29 and thesecond metal film 42 has to be selected. Therefore, the degree offreedom in the material selection of the capacitance insulating film 27is narrowed. Accordingly, the above-described capacitor structure of thepresent embodiment also has the effect of solving such a problem.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

The present invention can be applied to a semiconductor device whichrequires a high-capacitance and high-accuracy MIM electrostaticcapacitor such as analog-digital LSI.

What is claimed is:
 1. A method for manufacturing a semiconductor devicehaving an electrostatic capacitor with a MIM structure including a lowerelectrode, a capacitance insulating film and an upper electrode formedon a semiconductor substrate, wherein a step of forming theelectrostatic capacitor includes: (a) a step of patterning a first metalfilm formed on a first interlayer insulating film on the semiconductorsubstrate, thereby forming the lower electrode; (b) a step of forming asecond interlayer insulating film on the first interlayer insulatingfilm and the lower electrode; (c) a step of forming an opening part in apart of the second interlayer insulating film, thereby causing a surfaceof the lower electrode to be exposed from a bottom surface of theopening part; (d) a step of forming the capacitance insulating film soas to cover an upper part of the second interlayer insulating film and aside wall and the bottom surface of the opening part; (e) a step ofsequentially forming a second metal film and a protective metal film onthe capacitance insulating film, thereby filling the opening part withthe protective metal film; (f) a step of polishing and removing theprotective metal film and the second metal film on the second interlayerinsulating film by a chemical mechanical polishing method, therebycausing the capacitance insulating film, the upper electrode made of thesecond metal film and the protective metal film to remain in the openingpart and causing the capacitance insulating film to remain on the secondinterlayer insulating film; and (g) a step of forming a third interlayerinsulating film on the second interlayer insulating film.
 2. The methodfor manufacturing the semiconductor device according to claim 1, whereinthe step (a) further includes a step of patterning the first metal film,thereby forming lower-layer wiring on the first interlayer insulatingfilm.
 3. The method for manufacturing the semiconductor device accordingto claim 1, further comprising: a step of etching the capacitanceinsulating film remaining on the second interlayer insulating film withusing a photoresist film covering an upper part of the opening part as amask.
 4. The method for manufacturing the semiconductor device accordingto claim 1, wherein the step (a) includes: (a-1) a step of forming awiring trench in a part of the first interlayer insulating film; (a-2) astep of depositing the first metal film on the first interlayerinsulating film and in the wiring trench, thereby filling an interior ofthe wiring trench with the first metal film; and (a-3) a step ofpolishing and removing the first metal film on the first interlayerinsulating film by a chemical mechanical polishing method, therebyforming the lower electrode having the first metal film in the wiringtrench.
 5. The method for manufacturing the semiconductor deviceaccording to claim 4, wherein the first metal film includes a metal filmcontaining copper, and the method further includes a step of forming aninsulating film for preventing diffusion of the copper on the firstinterlayer insulating film after the step (a-3).
 6. The method formanufacturing the semiconductor device according to claim 1, furthercomprising: after the step (g), (h) a step of forming a first contacthole in the third interlayer insulating film and forming a metal plug inthe first contact hole; and (i) a step of forming first upper-layerwiring on the third interlayer insulating film and electricallyconnecting the first upper-layer wiring and the protective metal film inthe opening part via the metal plug in the first contact hole.
 7. Themethod for manufacturing the semiconductor device according to claim 6,wherein the step (h) further includes a step of forming a second contacthole in the third interlayer insulating film and the second interlayerinsulating film and forming a metal plug in the second contact hole, andthe step (i) further includes a step of forming second upper-layerwiring on the third interlayer insulating film and electricallyconnecting the second upper-layer wiring and the lower electrode via themetal plug in the second contact hole.